• CEO Dr. Wang Wen Hsiang
• Ph.D. of National Taiwan University Geological Institute.
• Formal Chairman of Taiwan Geological PE Association.
• Chair Professor of China University of Geoscience(Wu Han).
• Committee Member of Land Usage Change of Taiwan Government.
• Now executed several Wafer Fabrication and Integrated Circuit design projects for Silicon Carbide, Gallium Nitrite and other new semiconductor materials projects.

Education

• Ph. D. of EE, SUNY at Stony Brook, USA (1992)
• MS of EE, SUNY at Stony Brook, USA (1988)
• BS of EE, NTU (1984)

• VP, Office of Research and Development, NSYSU
• Dean, College of Engineering, NSYSU
• VP, Office of Industrial Collaboration and Continuing Education Affairs, NSYSU
• CEO, Operation Center of University-Industry Cooperation, NSYSU
• Chairman, Dept. of EE, NSYSU
• Program Director, NSOC and NPIE

Publications : >160 journal papers, 320 conf. papers, 180 patents.
Technology Transfer : 20 items, > 1 MUSD

Honors (selected)

• ASE Chair Professor
• Distinguished Professor
• IET Fellow
• Best paper awards : 2008 IEEE ICCE, 2011 IEEE PrimeAsia, 2017 IEEE ICDV, 2019 IEEE ISOCC, 2021 IEEE ICICDT
• Distinguished Lecturer of IEEE (2019-2021)
• Future Tech. Award (2021)
• Top 2% Researcher/Scientist in the world by Stanford U. report (2021, 2022)
• Adjunct Professor, Vel Tech U., India (2022 – 2024)

International Academia Services (selected)

• General Co-Chair, 2010 IEEE ISNE
• Conference Chair, 2011 IEEE International Conference on IC Design and Technology (ICICDT)
• General Chair of 2012 Asia Pacific Conf. on Circuits and Systems (APCCAS)
• General Chair, 2015 Symp. On Engineering, Medicine and Biology Applications (SEMBA)
• First Taiwan-Philippines Joint Workshop (2017)
• First Taiwan IC Design Course Teaching Team to Philippines (2017)

China Team Leader: Mr. Wang Chaojen

Mr. Wang Chaojen, graduated from National Taiwan University Civil Engineering, the general manager and stockholder of Zhaoke Electronic Technology company(ZETC). He was invited by SMIC (Semiconductor Manufacturing International Corporation, 00981.HK/688981.SH) to establish hundreds of clean rooms for semiconductor wafer production, IC packaging, and test factories during 2007 to 2009. He has lead teams consisting of thousands of employees, contractors, suppliers, workers under my strict supervision. Thus, He has strong leadership in many assembly, package, and testing (APT) factory construction & management.

Primary business of Zhaoke Electronic Technology Company (ZETC) is MCUs, IC component assembly, packaging and test (APT), which is located at Bengbu city, Anhui province, China, hires more than 800 employees. ZETC capital size is planned to be 1 billion RMB (150 million USD) after two rounds of funding with Soft Bank (China) in 2023. And ZETC plans to IPO in China and Singapore in next 3 to 5 years.



China Team CTO: Dr. Danny Liu

• Education
• Ph.D Materials California Institute of Technology Pasadena Ca. USA (NASA JPL/ Teledyne Scholarship (1990-1994))
• MSEE Northrop-Grumman University L.A. Ca. USA 1989 MSCS California State University at Northridge (CSUN) Northridge Ca. USA 1988 BSEE & CE Oregon St. University Corvallis, Or. USA 1982
• (Harcourt Brown Fellowship from University College (1978))
•  Working Experience

• CEO Symphony Science & Technology Co. Chuzhou, Anhui 2018-Present
• (Power chips/ Modules/PCBA design house)
• CEO Wuxie Crystal Advanced Technology Co.
• (Chip & Module assembly & Test house: subsidiaries of Symphony Science & Technology company)
• CEO Xcyclone Advanced Technology Co. Suzhou, JiangSu 2016-2018
• (IPM(Intelligent Power Module design house)

Consultant O-Film Technology Co. Nanchang, Jiangxi 2015-2016
(Image sensor module design & Mfg. House, 23000 employees)
Managing Director Hong Kong Nantai Electronics Co. Shenzhen, Guangdoing 2010-2015
(EMS, 9300 employees)
GM & Plant Director ONSemi Co. Chengdu, Sichuan 2007-2010
(Chips assembly & test plant, 1600 employees）
CEO & Founder CamTech. Co. Taiwan & Kunshen 2004-2006
(Image sensor chips & module design & assembly house)
Sr. Manager SMIC Shanghai 2001-2002
(Wafer processing: Etching Dept.)
CEO & Founder Advanced Semiconductor Inc. Hsinchu, Taiwan 1997-2000
(Chips & Module of Assembly & Test house)
CEO Korea Advanced Semiconductor Inc. Korea 1998-2000
(ASI J/V with Hynix-Hyundai Group, Korea; Flash memory assembly & test house)

Sr. Manager WaferTech(TSMC) Wash. USA 1997-1998
(8’ Fab. 0.35um Etching Dept.)
& Consultant Fab. 6 (TSMC) Taiwan
VP & Test Plant Director Advanced Semiconductor Engineering Group Taiwan, 1994-1997
(Chips assembly & Test Company)
ASIC Design Manager Advantest Co./JPL NASA Pasadena USA 1989-1994
(Mixed-signal Tester design for US Navy & NASA JPL use)
GaAs Hybrid design Manager Teledyne System Co. Northridge Ca.USA 1986-1989
(Military project design & MFG.)
ASIC design Engr.(Gate Array Div) Gould AMI Co. Santa Clara, Ca.USA 1984-1986
(IDM company)
Design Engr.(CPU Group) intel Co. Santa Clara, Ca. USA 1982-1984
(CPU 80X86 Group)
Wafer Process(intern) intel Co. Hillsboro, Or. 1981 summer (3” Fab.)
Wafer testing(WAT) (intern) Hewlett-Packard Corvallis, Or. 1980 summer (3” Fab.)